An important digital baseband communication system is found in the read channel of a magnetic storage system of a conventional computer hard disk drive (HDD). HDD read/write channels use partial response maximum likelihood (PRML) techniques to increase the bit density on the disk. Uncoded binary data from a computer is not suitable for recording on a PRML disk drive because unconstrained computer data could contain long spans of adjacent zeros. Such long spans of zeros provides no timing or gain information for the read channel, thereby preventing the proper timing and gaintracking for the read back signal waveform. Encoding data to provide run length limited (RLL) data has therefore become common. RLL Coding schemes use (d,k) constraints which limit the minimum and maximum run lengths of zeros respectively, or alternatively they control the high and low frequency contents of the user data.
Conventional high-rate RLL (0,k) codes are highly complex for circuit implementation and relatively "blind" in terms of error detection during the demodulation process. The d, k constraints comprise the only properties of these codes exploitable for error control purposes. However, this specialized type of error is only a small subset of the total number of possible errors. Furthermore, the conventional codes are of fixed codeword length/code rate requiring complete redesign of the encoder/decoder for a higher code rate.
The design of modulation codes with coding gain for read channels in HDDs is mainly focused in two different directions, first, to enhance error/erasure control capabilities, and second, to enhance the detectors performance.
A. Enhance Error/Erasure Control Capabilities
Concatenation of conventional RLL with ECC can reduce the effectiveness of the ECC, especially with a sliding block encoder/decoder subject to limited error propagation. RLL codes with error-detecting capabilites which have been reported are also of a lower rate than the conventional 8/9, and 16/17 RLL codes.
For RLL(d=0,k/l) codes, optimal block codes with gated-partition logic and high rates such as 8/9 and 16/17 have been demonstrated while focusing on the k-constraint of the maximum run-length of consecutive 0s for timing recovery purposes, and the interleave constraint "l" to eliminate quasicatastrophic sequences. The very limited error control capability of the code is exclusively associated with the k, l-global and interleave constraints respectively. See U.S. Pat. No. 4,707,681 to Eggenberger and Patel, and Patel, A. M. "Rate 16/17(0,6/6) Code," IBM Tech. Disclosure Bull. 38, 8 1989; both incorporated herein by reference.
In "A class of (d,k) block codes with single error-correcting capability", Digests Intermag '97, by P. H Liu and Y. Lin, the design objective was a modulation encoder generating encoded sequences of a specific minimum distance with single error-correcting capability. However the obtained code rates are lower than those of the conventional RLL ones, and some of the reported code rates are in the order of 8/21, 8/28.
In "The (d,k) Subcode of a Linear Block Code", IEEE Trans. On Info. Thy., vol. 38, no. 4, pp. 1375-1382, July 1992, Papoutian and Kumar proposed that the block length of the Hamming subcode is kept as large as possible to avoid rate loss for a single-error correcting ECC/RLL code.
In "Error and Erasure Control (d,k) Block Codes", IEEE Trans. On Info. Thy, vol. 37, no. 5, September 1991; Ferreira and Lin demonstrate redundancy based on appended parity bits is used, or access to channel-side information is possible and sufficiently long codewords are assumed in order to construct high rate combined codes with single error correction capability.
Construction of systematic RLL codes capable of single error-detection causes rate loss and produces less efficient codes than nonsystematic ones. The required number of parity check bits attached to an RLL encoded sequence is equal to d+3. See "RLL codes for single error detection in the Magnetic Recording Channel", IEEE Trans. On Info. Thy., vol 41, no. 3, May 1995. This can be shown by starting with an RLL code of rate=n/m then the resulting final code rate will be equal to ##EQU1## For example, use of just one appended parity check bit would create RLL code rates in the order of n/(n+2) which are lower than n/(n+1).
In "Error Detecting Runlength-limited Sequences", IEEE Video, Audio & Data Recording, by K. A. S. Immink, it was stated that in order to alleviate the overhead on the code rate due to the appended parity, an increase of the codeword length should be applied (approximately 3 to 4 times larger than conventional RLL with the same rate) increasing however the system's probability of error. It was also proposed to choose the only odd or only even sequences (whichever would provide the needed number of codewords) satisfying d, k constraints, and apply parity checking in order to avoid addition of extra parity check bits with a code rate reduction effect. However, in the above, not all rates are feasible for every codeword length due to insufficient number of available codewords.
B. Enhance the Detector's Performance
MTR codes are of lower rate than RLL (up to maximum 6/7), while their objective is to limit the number of transitions to increase the d.sub.min between the generated sequence. Then a gain is produced at the E.sup.2 PR4 detector by eliminating the minimum distance error event. The reported 4/5, 5/6 and 6/7 MTR codes have made use of look-ahead encoders/decoders, and there is an associated error-propagation problem. See B. Brickner and J. Moon, "Design of a rate 6/7 Maximum Transition Rate Code", IEEE Trans. On Magnetics, pp. 2749-2751, September 1997. Time varying MTR schemes are of maximum code rate equal to 8/9, requiring time-varying detector of higher complexity. The associated detector gain for both MTR and TMTR is at maximum equal to 2.2 dB for E.sup.2 PR4 systems. See W. Bliss, "An 8/9 Rate Time-varying Trellis code for high density magnetic recording", Digests Intermag '97.